1. Field of the Invention
This invention relates to an electrically rewritable semiconductor memory device.
2. Description of the Related Art
Various types of electrically rewritable non-volatile semiconductor memory devices including electrically erasable programmable read-only memory (EEPROM) chips have been developed. Memory cells of the type having metal oxide semiconductor field effect transistor (MOSFET) structures are such that each cell stores as digital bit information electrical charge which was injected from a channel into a charge accumulation or storage layer through an insulative film by the flow of a tunnelling current, wherein the information thus stored is readable by measurement of a change in conductance of the MOSFET in accordance with the amount of such electrical charge. “NAND” type EEPROMs and “AND” type EEPROMs, inter alia, are the ones with cell units each made up of a serial or parallel combination of a plurality of memory cells. These NAND/AND-EEPROMs are capable of more significantly reducing the number of select transistor gates than that of memory cells, thus offering an ability to much increase the resulting on-chip integration density.
Large-capacity NAND-EEPROMs are typically arranged to have a plurality of cell units laid out in a row direction (that is, data select line direction) and a column direction (i.e. data transfer line direction). A group of the cell units aligned in the row direction constitutes a cell block, which generally becomes a unit for “all-at-a-time” or “all-at-once” data erase. Additionally, the memory cell array of a NAND-EEPROM chip is typically designed to include a normal cell array that is used to perform ordinary or regular data storage and a redundant cell array used for execution of defective column replacement. The redundant cell array is disposed at a one end portion of the normal cell array along the data select line direction. A data select line driver is provided to drive data select lines of each cell block. Regarding this driver, a scheme has been proposed for subdividing driver circuitry into portions which are alternately disposed on the opposite sides of the memory cell array, in order to facilitate on-chip layout design while at the same time equalizing skews between data select lines. In this respect, a typical approach using this concept is disclosed, for example, in Published Unexamined Japanese Patent Application No. 2000-76880 (“JP-A-2000-76880”).
Prior known data select line layout schemes and circuit configurations employable in NAND-EEPROM chips are disclosed, for example, in Japanese patent documents JP-A-2000-76880 and JP-A-2001-150784. As for sense amplifier and redundancy circuit arrangements, teachings are found in JP-A-2001-167592 and JP-A-2000-21190 and also in U.S. Pat. No. 6,421,272. A technique for setting an initial setup data storage area in the cell array is disclosed in JP-A-2001-176290.
Increasing the integration density of memory cell array by miniaturizing the cell size of NAND-EEPROM chips while lengthening data select lines for common connection of the control gates of memory cells, the data select lines (gate wiring leads) increase in electrical resistance, resulting in an increase in delay of voltage signal transmission on such on-chip lead wires—namely, “wire delay”—becomes greater. Due to this, a need is felt to specifically design timing pulse signals used to drive the data select lines during read and write sessions in such a way as to provide a specific length of time period required for enabling successful execution of any intended read/write operations relative to all the memory cells as laid out along the data select lines. Unfortunately, this serves as a bar for acceleration of read/write operations. This wire delay problem will be discussed in detail below.
See FIG. 41. This diagram illustrates part of a NAND-EEPROM chip, which includes NAND cell units 49a to 49c that are driven by a single data select line driver 2. The cell units 49a–49b are included in a normal cell array 100 for execution of ordinary data storage, while the other cell units 49c are in a redundant cell array 101. These normal cell array 100 and redundant cell array 101 are operatively associated with data select lines (word lines) WL0 to WL15 and select gate lines SSL and GSL, which are driven by the data select line driver 2 that is laid out on one side of the normal cell array 100.
Here, an explanation will be given under an assumption that a data select line WL14 is presently selected during data reading. This selected data select line WL14 is applied a read voltage Vref that is necessary for cell data determination, whereas the remaining, non-selected data select lines WL0–WL13 and WL15 are given a pass voltage Vread which is required to cause memory cells to turn on without regard to whether the cell data of interest is a logic “0” or “1”.
FIG. 42 shows the waveforms of voltage signals appearing at circuit nodes A and B on one nonselected data select line WL15 and also at nodes C and D on the selected data select line WL14 during reading. The voltage waveforms of the other nonselected data select lines WL0–WL13 are almost the same as those of the nonselected data select line WL15. The nodes A and C are the ones that are in close proximity to the data select line driver 2 within the normal cell array 100; and the nodes B, D are the furthest nodes from the data select line driver 2 within the redundant cell array 101.
A voltage of the node A on the data select line WL15 is adjacent to the data select line driver 2 so that it starts up from ground potential GND at a timing t0 and then potentially rises up to Vread almost at timing t1′ as indicated by a broken line in FIG. 42. The node B on the same data select line WL15 is far from the data select line driver 2 so that the lead wire's CR time constant is large in value; thus, node B potentially starts up from GND at timing t0 and thereafter rises up to Vread at timing t1, with a delay from timing t1′ as indicated by solid line.
In a case that the capacitance between the data select line of interest and a substrate is the most dominant one among all the capacitances of the data select lines concerned, a ratio of (t1′−t0) to (t1−t0) becomes substantially equal to a ratio of a squared value of the length of a portion of data select line which extends from the data select line driver 2 to node A versus a squared length of another portion of the data select line spanning from data select line driver 2 to node B. Hence, as the data select line increases in length, the delay time of potential rise-up increases in proportion to a squared value of the length thereof.
The selected data select line WL14 is kept at the read voltage Vref that is lower in potential than the pass voltage Vread, in responding to receipt of an output of the data select line driver 2. However, at the time of rise-up of pass voltage Vread, the data select line WL14 increases in potential by the presence of capacitive coupling from its neighboring data select lines WL15 and WL13. As shown in FIG. 42, while this voltage increase at the node C near data select line driver 2 is less, the node D that is far from data select line driver 2 is such that its voltage rise-up becomes larger because the wiring capacitance and wire resistance of data select line driver 2 of the neighboring data select lines WL15 and WL13 become larger in value.
At the node A, after the timing t1′, the voltage Vread of data select lines WL13 and WL15 is held at a constant value. Due to this, the data select line WL14 exhibits no further voltage increment and is discharged through the data select line driver 2. The node C returns almost to Vref at timing t2′; and the node D returns almost to Vref at timing t2 with a delay therefrom. In a case that the capacitance between the data select line and substrate is the most dominant one among all the data select line capacitances, a ratio of (t2′−t1′) to (t2−t1) is substantially equal to a ratio of a squared value of the length of a portion of data select line which extends from the data select line driver 2 to node C versus a squared length of another portion of data select line spanning from data select line driver 2 to node D. Hence, as the data select line increases in length, the delay time of the rise-up of a potential variation of data select line WL14 increases in proportion to the squared value of its length. Since the current of a memory cell is determinable by a difference between the memory cell's threshold voltage and the read voltage Vref, it is necessary to measure the memory cell current exactly after this read voltage Vref becomes constant.
Thereafter, letting the pass voltage Vread drop down to ground potential GND at timing t3, the reading is ended. At this time, the node A of data select line WL15 near the data select line driver 2 potentially decreases to GND at timing t4′, while the node B far from data select line driver 2 drops down to GND at timing t4 with a delay therefrom. In case the capacitance between the data select line and substrate is the most dominant among all the capacitances of the data select lines, a ratio of (t4′−t3) to (t4−t3) becomes substantially equal to a ratio of a squared value of the length of a portion of data select line which extends from the data select line driver 2 to node A versus a squared length of another portion of the data select line spanning from data select line driver 2 to node B. Thus, the longer the data select line, the greater the delay time of potential rise-up in a way proportional to the squared value of its length.
As apparent from the foregoing discussion, a time range T2 necessary for memory cell readout of the NAND cell unit 49c that is far from the data select line driver 2 is from t2 to t3; and a time range T1 required for memory cell readout of the NAND cell unit 49a that is near data select line driver 2 is from t2′ to t3. Unfortunately with prior art read methods for merely reading the cell units 49a to 49c together at a time, the actual read time is limited to the read time range T2 of NAND cell unit 49c. Thus a longer read cycle time is required.
Although specific pulses during reading are indicated in FIG. 42, the same goes with writing—that is, those memory cells of a NAND cell unit distant from the data select line driver 2 require consumption of longer rise-up and fall-down time periods of a write pulse voltage. Thus, a long write cycle time should be required, which is limited to the memory cells furthest from data select line driver 2.
Further, when using memory cells (spare column) within the redundant cell array 101 to replace a column that includes a defective memory cell or cells within the normal cell array 100, there is a possibility that a defective column of the NAND cell unit 49a nearest to the data select line driver 2 is replaced with a column of the NAND cell unit 49c furthest from data select line driver 2. Hence, it is required to secure or “reserve” large timing margins to thereby guarantee that the intended read and write operations are executable both in the memory cells of the NAND cell unit 49c furthest from the data select line driver 2 and in those of the NAND cell unit 49a nearest to this driver 2.
Having stated above, in semiconductor memory chips of the type having a matrix layout of multiple cell units each having a serial or parallel combination of memory cells, an increase in number of cell units with an increase in length of data select lines does not come without accompanying a penalty: an unwanted increase in time margins as required until settlement of potential stabilization of read and write pulse voltages at certain memory cells far from the data select line driver operatively associated therewith, because of voltage transfer delays occurring due to the presence of capacitive coupling between data select lines and the CR time constant of these data select lines. This makes it difficult to speed up the write and read operations. Furthermore, in the case where the spare column of redundant cell array is used to replace a defective column within the normal cell array, it should be strictly required to settle increased timing margins in such a way as to enable successful achievement of read and write operations at both the memory cells furthest from the data select line driver and those nearest thereto.